• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A 3D circuit design method includes: providing circuit design files (410) representing a 3D circuit design comprising one or more macros each having a property allowing other circuit elements to be superimposed thereon; by means of the circuit design tool (402, 404), placing and routing comprising at least partially the superposition of one or more logic cells on said one or more macros and the routing of connections between said one or more logic cells and 3D interconnection pads defined on faces of said one or more macros; and generating a final 3D circuit layout by extracting from the 3D circuit layout a first circuit layout of a first level comprising said one or more logic cells and a second circuit layout of a second level comprising said one or more macros.
    公开号:FR3082638A1
    申请号:FR1855326
    申请日:2018-06-18
    公开日:2019-12-20
    发明作者:Sebastien Thuries；Olivier Billoint；Didier Lattard；Pascal Vivet
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    DESIGN OF A 3D CIRCUIT INCLUDING MACROS
    Field of the invention
    The present description relates to the field of 3D circuit design, and in particular a method and a computer device for generating a 3D circuit layout using a 2D circuit design tool.
    Presentation of the prior art
    During the design of an integrated circuit comprising millions of transistors, a key phase of the design process is the physical implementation operation involving synthesis of the circuit and placement-routing. During this operation, a file representing the circuit to be manufactured, such as a GDS file (from the English Graphie Database System), is generated by a dedicated design tool. The design tool, for example, performs a circuit synthesis to generate an implementation at the door level, then places the cells of the circuit design on the available surface of the integrated circuit. A routing algorithm is then applied to interconnect the cells of the circuit design to create a circuit layout.
    B16909 - DD18558ST
    3D circuits, in which cells are arranged on multiple stacked levels interconnected by interconnections such as 3D vias, provide many advantages in terms of compactness and performance of the circuits.
    There are various technologies that can be used to make 3D circuits. For example, some of these technologies are based on the fabrication of several 2D circuits, which are then stacked in a face-to-face, face-to-back, or back-to-back arrangement, or stacked using a mixture of these interfaces. The face of an integrated circuit corresponds to the side closest to the metal interconnection levels, while the back corresponds to the side closest to the substrate, generally made of silicon.
    Another technology, known as monolithic 3D transistor technology, and also known as sequential 3D and CoolCube ™, involves the fabrication of a plurality of self-contained transistor levels. In particular, two or more levels of transistors are formed sequentially and interconnected by vertical 3D vias corresponding to a face-to-back arrangement. For example, this technology is described in more detail in the publication by P. Batude et al. titled 3D sequential integration opportunities and technology optimization, IEEE International Interconnect Technology Conference, 2014, pages 373-376. An advantage of monolithic 3D technology is that the silicon thicknesses of each level can be relatively small, which allows a high density of interconnections between the levels.
    One problem in designing 3D circuits is that existing software tools implementing placement and routing have been developed for 2D circuits, and are not compatible with the generation of high density 3D circuit designs. In addition, the creation of a new design tool designed for the design of 3D circuits would be time consuming and costly.
    B16909 - DD18558ST
    There is therefore a need in the art for a method and a circuit design device allowing the design of 3D circuits having a relatively high density.
    summary
    An object of embodiments of the present description is to at least partially solve one or more needs of the prior art.
    In one aspect, there is provided a 3D circuit design method comprising: providing, to a circuit design tool, circuit design files representing a 3D circuit design comprising one or more macros each having a property that allows other circuit elements are superimposed on it; perform, by the circuit design tool, placement and routing of the 3D circuit design to generate a 3D circuit layout of the 3D circuit design, the placement and routing comprising at least partially the superposition of a or several logic cells on said one or more macros and the routing of connections between said one or more logic cells and 3D interconnection pads defined on faces of said one or more macros; and generating a final 3D circuit layout by extracting, from the 3D circuit layout, a first circuit layout of a first level comprising said one or more logic cells and a second circuit layout of a second level comprising said one or more multiple macros.
    According to one embodiment, the method further comprises transmitting the final 3D circuit layout of the 3D circuit design to a production site for its manufacture.
    According to one embodiment, the method further comprises manufacturing a 3D circuit design based on the final 3D circuit layout.
    According to one embodiment, each of said one or more macros comprises a superposition layer defining a region of each macro to which other circuits can be superimposed.
    B16909 - DD18558ST
    According to one embodiment, said one or more macros are defined in the circuit design files as being encapsulated in a higher level in which the 3D interconnection pads are present.
    According to one embodiment, the 3D circuit layout comprises one or more levels comprising only the macros.
    According to one embodiment, the method further comprises, before performing the placement and routing, a synthesis operation during which a functional definition of a logic circuit of the 3D circuit design is translated into a list of connections defining said circuits. one or more logical cells.
    According to one embodiment, the synthesis operation is based on a preplacement of said one or more macros on a 3D layout plan.
    According to another aspect, a circuit design system is provided comprising one or more processors and one or more memories storing software instructions which cause said one or more processors to implement the aforementioned method.
    According to another aspect, there is provided a non-transient storage medium storing software instructions which cause the above-mentioned method to be implemented when the instructions are executed by one or more processors. Brief description of the drawings
    The aforementioned characteristics and advantages and others will appear clearly with the following detailed description of embodiments, given by way of illustration and not by limitation, with reference to the attached drawings in which:
    Figure 1 is a sectional view of a 3D circuit according to an example of arrangement face against back;
    Figure 2 is a sectional view of a stack of integrated circuits according to an example;
    B16909 - DD18558ST FIG. 3A illustrates a 3D circuit according to an exemplary embodiment of the present description;
    FIG. 3B is a plan view of a 2D circuit design comprising logic cells and macro circuits;
    FIG. 3C is a plan view of layers of a 3D circuit design comprising a layer of logic cells and another layer of macros;
    FIG. 4 schematically illustrates a system for designing 3D circuits according to an exemplary embodiment of the present description;
    FIG. 5 is a flowchart representing steps in a method for designing a 3D circuit according to an exemplary embodiment of the present description;
    Figure 6A is a flat view of a macro including an overlay;
    FIG. 6B is a flat view of 3D interconnection pads of the macro of FIG. 6A;
    FIG. 7A illustrates a layout plan of a 3D circuit according to an exemplary embodiment of the present description;
    FIG. 7B illustrates the 3D circuit of FIG. 7A during the placement-routing according to an exemplary embodiment of the present description; and FIG. 8 is a sectional view of a 3D circuit comprising a logic circuit superimposed on a macro according to an exemplary embodiment of the present description.
    detailed description
    Figure 1 is a sectional view of a monolithic 3D circuit 100 according to an exemplary embodiment. The circuit 100 comprises for example a level 102 of transistors formed on a handle layer 101, and another level 104 of transistors formed above the level 102. An intermediate metallic interconnection layer 106 is used for example to ensure interconnections between transistor devices 108 of levels 102, 104.
    B16909 - DD18558ST
    Although this is not illustrated in FIG. 1, another metallic interconnection layer could be provided above the level 104. Examples of 3D vias 110, 112 are also illustrated, known as monolithic inter-level vias (MIV).
    FIG. 2 is a sectional view of a 3D circuit 200 comprising a stack of integrated circuits, comprising face-to-face, back-to-back and back-to-face interfaces between the sides of the top (FACE) and the sides of the bottom (BACK ) circuits. In the example of FIG. 2, there are five integrated circuits forming corresponding levels referenced T1 (lower level) to T5 (upper level). Each integrated circuit comprises for example a substrate layer (SUBSTRATE) 202 constituted for example of silicon, a layer of transistors (TRANSISTORS) 204 or FEOL (front end of line) and a layer of metallic interconnections (METALS) 206 or BEOL ( rear end of line) comprising one or more metallic levels, examples of layers Ml and MX are shown in the figure
    2. The substrates 202 of the levels T1 to T4 have for example been thinned. Where the rear side is used as an interface, TSVs (vias through silicon) 208 are for example used to form connections between the metal layer 206 and the rear side. The lower level T1 in the stack comprises for example bosses 210 for connecting the stack to a circuit board (not illustrated in FIG. 2).
    FIG. 3A illustrates a 3D circuit 300 according to an exemplary embodiment of the present description. The 3D circuit 300 can for example be considered as a high density 3D circuit, implying a 3D circuit comprising a stack of levels (chips or layers in a monolithic circuit) in which 3D vias have a diameter equal to or less than 5 pm.
    The present inventors have noticed that in digital circuits or mixed digital / analog circuits, the surface occupied by logic cells, that is to say standard cells, generally goes up to 50%. The rest is occupied by larger macro circuits, sometimes called
    B16909 - DD18558ST IP circuits (from the English Intellectual Property - intellectual property).
    As is known to those skilled in the art, logic cells are relatively small circuits comprising digital logic devices which are used to implement Boolean logic functions, such as AND, OR, NON OR, OR EXCLUSIVE gates and NOT OR EXCLUSIVE, or basic memory functions, such as locks and flip-flops. These logic cells are generated by the circuit design tool during a synthesis operation based on code defining the functionality of the logic cells, for example in the form of RTL code (from the Register Register Level transfer level of registers) . Each logic cell is for example selected from a library of standard cells, and the selection, during the synthesis of the circuit, of the particular standard cell for implementing each logic function can be based not only on the logic function, but also on d other factors such as available space, positioning of macros and other logical cells, etc. In some embodiments, this selection can be changed during the placement and routing operation.
    As is also known in the art, macros are generally larger circuits which may include logic cell circuits, memories and / or other circuits including analog circuits. The design of a macro, including the positioning in the macro of the various cells of the macro and the interconnections between these cells, can be considered as fixed, in other words, it is not modified during the synthesis of the circuit and the placement and routing operations.
    As shown in FIG. 3A, according to embodiments of the present description, the 3D circuit 300 is for example designed to have one of its levels, the lower level Tl in the example of FIG. 3A, containing only logical cells, or a mixture of logical cells and
    B16909 - DD18558ST some macros (LOGIC (+ MACROS)), and to have one or more levels containing only macros. In the example of FIG. 3A, there are levels T2 and T3 containing only macros (MACROS).
    The 3D circuit 300 could for example be formed using a monolithic 3D sequential technology as described above in relation to FIG. 1, which corresponds to the use of back-to-face interfaces between the levels. Alternatively, it could be formed by stacking two or more integrated circuits using back-to-back, face-to-face, and / or back-to-face interfaces, as previously described in connection with Figure 2, or by mixing of the technologies of FIGS. 1 and 2. In addition, in the case where two or more integrated circuits are stacked, each of these circuits can be formed using a different transistor and metallization technology (Back End of Line) ).
    Figure 3B is a plan view illustrating an example of a circuit layout 350 which has been generated assuming that the circuit design is to be generated as a 2D circuit. The circuit design includes, for example, macros 352, of which ten having various sizes are found in the example of Figure 3B. A logic circuit 354 made up of standard cells, represented by horizontal lines in FIG. 3B, is implemented in the space surrounding the macros 352.
    Figure 3C is a flat view illustrating an exemplary 3D design plot of the circuit design of Figure 3B, comprising two levels, a lower level 356 of logic and an upper level 358 of macros. In particular, level 356 comprises, for example, part or all of the logic circuit 354, while level 358 comprises, for example, all of the macros 352.
    Figure 4 schematically illustrates a 3D circuit design system 400 adapted to implement a method
    B16909 - DD18558ST 3D circuit design, for example the design of a 3D circuit similar to that of Figure 3A or 3C.
    The system 400 comprises for example one or more processors (P) 402 under the control of instructions stored in an instruction memory 404, which is for example a RAM, although in variant embodiments this may be another type of memory as a FLASH memory. For example, said one or more processors 402 are coupled, via a bus 406, to memory 404 and also to another memory (MEMORY) 408. Memory 408 is for example a non-volatile memory storing files circuit design (CIRCUIT DESIGN FILES) 410 representing macros and standard cells to be implemented in the 3D circuit. During the design of the 3D circuit, the memory 408 also stores for example one or more modified macros (MODIFIED MACRO (S)) 412, a hardware implementation (HARDWARE IMPLEMENTATION) 414 of the circuit design resulting from the synthesis of the files of circuit design 410, and the layout of the 3D circuit (3D CIRCUIT LAYOUT) 416 resulting from the placement and routing applied to the hardware implementation 414. In certain embodiments, the memories 404 and 408 could be implemented in a same memory device.
    The system 400 further comprises a communication interface (COMMS INTERFACE) 417, for example coupled to the bus 406, and by means of which the layout of the 3D circuit can be transmitted, for its manufacture, to a circuit manufacturing site integrated or to a semiconductor foundry (IC FABRICATION SITE) 420, via a communication link 418 including for example the Internet.
    Of course, although this is not shown in Figure 4, the system 400 could additionally include one or more user input devices, such as a keyboard, mouse, etc., one or more output devices such as a display.
    The memory 404 and / or the memory 408 store, for example, computer instructions for controlling said one
    B16909 - DD18558ST or several 402 processors to carry out a 3D circuit design method, comprising for example circuit synthesis and placement-routing steps. This combination of software and processing resources will be referred to herein as a 3D circuit design tool.
    We will now describe in more detail a method for generating a 3D circuit layout using the 3D circuit design tool of FIG. 4, with reference to FIG. 5.
    FIG. 5 is a flowchart illustrating an example of steps in a 3D circuit design method according to an exemplary embodiment of the present description. In particular, the 3D circuit is for example defined by a circuit layout of each level of the 3D circuit, represented for example in the format GDS (General Design Specification), or OASIS (Open Artwork System Interchange Standard norm d exchange for open graphics system). At least some of the steps of this method are implemented by the 3D circuit design tool of FIG. 4, except step 503, which is for example implemented by an operator of the design tool.
    It was assumed that initially the standard circuit design macros and cells are represented by the circuit design files 410 in Figure 4, and that these files were loaded into memory 408. The circuit design files 410 can for example be in Verilog or VHDL (VHSIC hardware description language, where VHSIC means very high speed integrated circuit) and can for example include:
    one or more LEF files (Library Exchange Format library exchange format) containing standard cell and macro information for design;
    - one or more LIB (Liberty Freedom) time files defining time models of standard cells and macros;
    B16909 - DD18558ST a DEF (Design Exchange Format) file defining placement information for standard macros and cells, and output (I / O) pins, and other physical components; and
    - one or more RTL files.
    In a step 501, physical properties of the circuit designs of one or more macros to be included in the 3D circuit design are modified, while respecting the targeted 3D technology, and in particular the pitch and the diameter of the 3D vias. For example, this implies an operation implemented by a computer consisting in modifying a LEF file associated with each macro to generate a LEF-3D file, and modifying a LIB file associated with each macro to generate a LIB3D file.
    This modification involves for example:
    - adding an overlay property to the macro; the offset of the macro pins to an upper interconnection layer of the device, for example to the HB layer (hybrid link layer), in order to maintain the connectivity of the macro pins and to ensure 3D vertical routing in the logic design 2D during placement routing; and
    - the encapsulation of the macro.
    As will be described in more detail below, following these modifications, the placement and routing can be carried out on the logic chips with the .lib-3D and .lef-3D files in order to obtain a setting relatively well optimized physical work of the 3D logic chip.
    As is known to those skilled in the art, the overlay property makes a circuit superimposable by other elements, and can be used to make free space available in a 2D circuit design. The present inventors propose to exploit this superposition property to allow algorithms for the placement and routing of standard 2D circuits to be used for the design of 3D circuits.
    B16909 - DD18558ST
    In particular, in the present description, the addition of the overlay property is used to make the macro superimposable by other elements such as standard cells, for example by modifying the macro LEF file. The overlay is for example defined as extending over the entire surface of the macro. In other words, the entire macro is defined as being superimposable by other circuits during the placement and routing operations. The operation of defining the overlay layer will now be described in more detail with reference to FIG. 6A.
    FIG. 6A is a flat view of a macro according to an exemplary embodiment, which for example represents a memory circuit. This circuit includes ground pins 602, supply voltage pins 604, and signal pins 606. A broken line rectangle 608 in Figure 6A represents the overlay, in other words the area in which the macro overlay is allowed. This region is for example defined by its border, which in the example of FIG. 6A corresponds to the border of the macro. This region is for example designed as an overlay layer by an indication in the properties of this region indicating that it must be considered as an overlay layer, for example by activating an appropriate flag. Although in the example of FIG. 6A the layer 608 extends over the entire surface of the macro, in other embodiments, certain regions of the macro could remain outside the region covered by the layer overlay, for example to allow 3D vias to pass through these regions.
    Referring again to FIG. 5, step 501 also implies for example the encapsulation of one or more macros in the upper level of the device, that is to say in the top of the BEOL stack of the circuit, which in some embodiments is a hybrid bonding layer (HB). Thus, the whole of the encapsulated macro (s) becomes a superposition layer to which other circuit elements can
    B16909 - DD18558ST be superimposed. In addition, by encapsulating each macro in the upper layer of the BEOL stack, the circuit design tool is forced to route to and from each macro via connections defined in this layer, rather than going to through lower metal levels.
    In addition, all of the input and output pins, including the signal pins and the power pins, are shifted to an upper face of the device, for example the HB layer, and are transformed into a suitable path to highlight works with 3D interconnection pads. An example of the implementation of this step will now be described in more detail with reference to FIG. 6B.
    FIG. 6B is a flat view of the macro 600 following the encapsulation of the macro in the metallic layer of the device, and the transfer of the power pins 602, 604 and the signal pins 606 to a higher level of the metallic layer, like level HB. The new connection pads replacing pins 602, 604 and 606 are referenced 602 ', 604' and 606 'respectively in Figure 6B. In addition, the electrical characterization of the macro, including the temporal characteristics of the signals, the heat dissipation, etc., defined for example in the LIB file associated with the macro, is for example modified on the basis of the new connection pads and of the new connections to these pads. These modifications are all for example operations implemented by computer which can be obtained by using designer scripts which depend on the intended 3D interconnection pitch and the diameter and in certain cases on the properties of the grid of the supply network, by example, of the size and the pitch of the tracks of the supply network.
    Referring again to FIG. 5, in a step 502, a synthesis of the circuit is carried out in a similar manner to a design of 2D circuits. This implies for example the processing of the circuit design files 410 of FIG. 4 in order to generate a hardware implementation of the
    B16909 - DD18558ST circuit design ready for placement-routing. For example, one or more RTL files representing logical functions are transformed into one or more lists of interconnections defining hardware implementations at the door level.
    In some embodiments, the circuit synthesis can be based not only on the circuit design of the logic circuit, but also on the modified macros generated in step 501. Indeed, although the macros cannot be modified in themselves during the circuit synthesis, certain physical aspects of the macros can impact the synthesis of the logic circuit. In addition, in certain embodiments, the synthesis can be based in part on a layout plan representing a macro pre-positioning generated in operation 503, as will now be described.
    In step 503, a 3D layout plan is for example defined for the 3D circuit. The 3D layout plan comprises for example a single level having the dimensions and the surface of one of the levels of the final 3D circuit layout. The 3D layout plan provides for example a preplacement of the macros of the 3D circuit. This pre-positioning is for example defined by an operator using an appropriate software application, or is provided to the design tool in the form of an electronic file. In some embodiments, supply rails of the circuit design are also pre-positioned during this operation. An example of macro placement in the design will now be described in more detail with reference to Figure 7A.
    FIG. 7A illustrates a 3D layout plan 700 representing an example of the preplacement of eight macros 702 to 709. Macros 702 to 708 must for example be placed in a higher level of the 3D circuit, and these macros correspond for example to macros modified in step 501 described above, which are stackable, encapsulated in an upper interconnection layer of the device, and include
    B16909 - DD18558ST 3D interconnection pads 710. The macro 709 must for example be placed in a lower level of the 3D circuit, with the logic circuit. Therefore, to avoid overlapping with the logic circuit, macro 709 is not modified to be superimposable, but can be superimposed on other macros. In the example of FIG. 7A, the macros 708 and 709 are partially superimposed between them.
    Referring again to FIG. 5, in a step 504, placement and post-placement optimization are then carried out, for example, on the basis of the 3D layout plan generated in step 503. During this step, the 3D interconnection pads of the macros created on the upper face of the device are treated as pins to be connected to pins of the logic circuit, and the circuit design tool realizes the placement of the cells of the logic circuit based on the locations of these 3D interconnection pads. The placement is for example based on known 2D placement algorithms which for example aim to place logic cells in a way which reduces the distances between the connected cells in order to reduce the lengths of wire. The placement and post-placement optimization operation will now be described in more detail with reference to FIG. 7B.
    FIG. 7B illustrates the 3D layout plan 700 of FIG. 7A during the placement step 504 of FIG. 5. As illustrated, certain logic cells 712, 714, 716, 718 and 720 have been placed, in superposition with macro 702, in view of connections between these logic cells and the 3D interconnection pads of macro 702 and macro 703.
    Referring again to FIG. 5, in a step 505, routing and post-routing optimization are for example carried out for said one or more macros and for the logic circuit. As explained above, the macros of the design being encapsulated in the upper layer of the device, the connections between the pins of the logic cells and the 3D interconnection pads of the macros are forced.
    B16909 - DD18558ST to pass through this upper layer, thus emulating 3D interconnections between logic cells and macros. In other words, while connections between logical cells in the design can pass between lower levels of the metallic layer, such as levels M1, M2, M3 or M4, connections between logical cells and macros always pass through the upper level of the device.
    For example, referring again to Figure 7B, a connection 722 between logic cells can pass through any metal layer, while connections 724 between logic cells and macros pass through the top layer of the device.
    Referring again to FIG. 5, in a step 506, the layout of the 3D circuit, represented for example by a GDS or OASIS file associated with each level of the 3D circuit, is for example transmitted to a production site for its manufacture and / or the 3D circuit is fabricated on the basis of the 3D circuit layer. The circuit layout of each level of the 3D circuit is for example extracted from the 3D circuit layout generated in steps 504 and 505. For example, this is obtained by separating, from the 3D circuit layout, a first circuit layout providing a view of an upper level of the 3D circuit including the final placement of the macros, and a second circuit layout providing a view of the lower level of the 3D circuit, comprising the logic cells and all the macros arranged in the lower level, with the macros superimposed removed.
    FIG. 8 is a sectional view of a portion 800 of a 3D circuit design resulting from the placement and routing operations 504 and 505 of FIG. 5. In particular, the circuit comprises for example a circuit 802 comprising the cells device logic (LOGIC CELLS), comprising an active layer (ACTIVE), and a metal layer comprising metal levels (Ml to M6), levels M7 and M8, power network layers L9 and L10 (SHARED POWER MESH LAYER), which are for example shared by adjacent levels of the 3D circuit, and a
    B16909 - DD18558ST hybrid bonding layer (HB). A macro 804 is superimposed on circuit 802, the elements of macro 804 which overlap circuit 802 being represented with broken lines and being referenced with text in italics in FIG. 8. In the example of FIG. 8, the macro is a SRAM having an active layer (ACTIVE), a metallic layer comprising 4 levels (Ml to M4) and a hybrid bonding layer (HB). FIG. 8 also represents the macro 804 in its encapsulation 806 and arranged face to face with the circuit 802, with the 3D interconnection pads of the HB layer of the circuit 802 contacting the 3D interconnection pads of the HB layer of the macro 804 .
    An advantage of the embodiments described here is that they overcome the main difficulties of designing, and in particular placing and routing, a 3D circuit design using a 2D circuit design tool. In particular, the method and the system described here make it possible to optimize the placement and routing by the design tool on the basis of the location of the 3D interconnection pads of the design macros, which are superimposed on the logic circuit. of the device.
    With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will readily appear to those skilled in the art. For example, although examples have been described on the basis of a face to face interface between levels of a 3D circuit, it will be clear to those skilled in the art that this method could be adapted to an interface face against back or back against back by defining one or more regions in which logic cells cannot be placed in order to provide space for vias through silicon, such as vias 110 or 112 in Figure 1, or vias 208 of Figure 2.
    In addition, it will be clear that although examples based on 3D circuits comprising only two levels have been described, the techniques described here could also be applied to 3D circuits comprising three or more levels.
    B16909 - DD18558ST in which one of the levels, like the lower level, comprises logical cells and optionally one or more macros, and the other levels include only macros. During the preplacement of these macros, the operator ensures for example that the macros of the same level are not superimposed and that enough free space is preserved for appropriate TSVs.
    In addition, it will be clear to those skilled in the art that the various elements described in relation to the various embodiments could be combined, in alternative embodiments, according to various combinations.
    权利要求:
    Claims (10)
    [1" id="c-fr-0001]
    1. A 3D circuit design method comprising: providing, to a circuit design tool (402, 404), circuit design files (410) representing a 3D circuit design comprising one or more macros (702 to 708) each comprising a property allowing other circuit elements to be superimposed on it;
    performing, by the circuit design tool (402, 404), placement and routing of the 3D circuit design to generate a 3D circuit layout of the 3D circuit design, the placement and routing comprising at least partially superimposing one or more logic cells on said one or more macros and routing connections between said one or more logic cells and 3D interconnection pads defined on faces of said one or more macros; and generating a final 3D circuit layout by extracting from the 3D circuit layout a first circuit layout of a first level comprising said one or more logic cells and a second circuit layout of a second level comprising said one or more macros.
    [2" id="c-fr-0002]
    2. Method according to claim 1, further comprising:
    transmit the final 3D circuit layout of the 3D circuit design to a production site for its manufacture.
    [3" id="c-fr-0003]
    The method of claim 1 or 2, further comprising fabricating a 3D circuit design based on the final 3D circuit layout.
    [4" id="c-fr-0004]
    The method according to any of claims 1 to 3, wherein each of said one or more macros includes an overlay layer (608) defining a region of each macro over which other circuits can be overlaid.
    [5" id="c-fr-0005]
    5. Method according to any one of claims 1 to 4, in which said one or more macros are defined in the circuit design files (410) as being encapsulated
    B16909 - DD18558ST in a higher level in which the 3D interconnection pads are present.
    [6" id="c-fr-0006]
    6. Method according to any one of claims 1 to 5, in which the 3D circuit layout comprises one or more levels comprising only the macros.
    [7" id="c-fr-0007]
    7. Method according to any one of claims 1 to 6, further comprising, before performing the placement and routing, a synthesis operation during which a functional definition of a logic circuit of the 3D circuit design is translated into a list of connections defining said one or more logical cells.
    [8" id="c-fr-0008]
    8. The method of claim 7, wherein the synthesis operation is based on a preplacement of said one or more macros on a 3D layout plan.
    [9" id="c-fr-0009]
    9. Circuit design system comprising:
    one or more processors (402); and one or more memories (404) storing software instructions which cause said one or more processors to implement the method of any of claims 1 to 8.
    [10" id="c-fr-0010]
    10. A non-transient storage medium storing software instructions which cause the method of any one of claims 1 to 8 to be implemented when the instructions are executed by one or more processors.
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    同族专利:
    公开号 | 公开日
    FR3082638B1|2021-07-02|
    EP3584724A1|2019-12-25|
    US20190384884A1|2019-12-19|
    US10997346B2|2021-05-04|
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    2019-12-20| PLSC| Search report ready|Effective date: 20191220 |
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    2021-06-30| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1855326A|FR3082638B1|2018-06-18|2018-06-18|DESIGN OF A 3D CIRCUIT INCLUDING MACROS|
    FR1855326|2018-06-18|FR1855326A| FR3082638B1|2018-06-18|2018-06-18|DESIGN OF A 3D CIRCUIT INCLUDING MACROS|
    US16/443,509| US10997346B2|2018-06-18|2019-06-17|Conception of a 3D circuit comprising macros|
    EP19180684.3A| EP3584724A1|2018-06-18|2019-06-17|Conception of a 3d circuit comprising macros|
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